1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device preferably applicable to flash memory, and a method of fabricating thereof.
2. Description of the Related Art
Flash memory is one known type of non-volatile semiconductor memory device. FIGS. 30 and 31 are a circuit diagram and a layout chart, respectively, showing a constitution of a NOR-type flash memory. FIG. 32A shows a schematic sectional view taken along the line I—I in FIG. 31, FIG. 32B is such that taken along the line II—II in FIG. 31, and FIG. 32C is such that taken along the line III—III in FIG. 31.
In the NOR-type flash memory (a first conventional example), as shown in FIGS. 30 and 31, a plurality of bit lines and a plurality of word lines are arranged so as to spatially cross with each other. The source and drain of a transistor composing one flash memory cell are respectively connected to either of two adjacent bit lines. Every bit line is commonly possessed by two adjacent transistors placed on both sides thereof. The gates of these transistors are connected to a word line. One transistor herein can store data at two points indicated in FIG. 30 with broken-line circles, that is, two bits are storable.
As shown in FIG. 31 and FIGS. 32A through 32C, the bit line is composed of a bit line impurity-diffused layer 4 formed in the surficial portion of a semiconductor substrate 1. On the other hand, the word line 6 is composed of a semiconductor film formed over the semiconductor substrate 1 while placing an insulating film in between. More specifically, an ONO film 2 is provided between a channel region (a portion of the semiconductor substrate 1) and the word line 6. The ONO film 2 comprises a silicon oxide film, a silicon nitride film and another silicon oxide film stacked in this order. Between the bit line impurity-diffused layer 4 and word line 6, a silicon oxide film 5 thicker than the ONO film 2 is provided. On the lateral faces of each word line 6, sidewalls 8 are formed (not shown in FIG. 31). An inter-layer insulating film 9 (not shown in FIG. 31) is formed over the entire surface. The area where neither the bit line impurity-diffused layer 4 nor the word line 6 is formed has a channel stop impurity-diffused layer 7 formed therein. That is, the channel stop impurity-diffused layer 7 is responsible for element isolation. A bit line contact 10 is formed in an insulating film, such as the silicon oxide film 5 on the bit line impurity-diffused layer 4 and the inter-layer insulating film 9, and a word line contact 11 is formed in an insulating film such as the inter-layer insulating film 9 on the word line 6. It is to be noted that illustration of the insulating films (ONO film 2, sidewall 8 and inter-layer insulating film 9) other than the silicon oxide film 5 on the bit line impurity-diffused layer 4 and a silicon nitride film 22 on the word line 6 are omitted in FIG. 31.
Next paragraphs will describe a conventional method of fabricating thus-composed flash memory (first conventional example). FIGS. 33A, 33B and 33C through FIGS. 37A, 37B and 37C are schematic sectional views for serially explaining a conventional method of fabricating the flash memory. It is to be noted that drawings having Fig. number suffixed by “A” are sectional views taken along the I—I line in FIG. 31, those having Fig. number suffixed by “B” are sectional views taken along the line II—II in FIG. 31, and those having Fig. number suffixed by “C” are sectional views taken along the line III—III in FIG. 31.
First as shown in FIGS. 33A through 33C, the ONO film 2 is formed on the surface of the semiconductor substrate 1. In the formation process of the ONO film 2, a silicon oxide film 2a having a thickness of 3 to 10 nm is grown, a silicon nitride film 2b having a thickness of 12 to 16 nm is formed thereon by the CVD process, and further thereon another silicon oxide film 2c having a thickness of 5 to 10 nm is grown by wet oxidation.
Next a resist film 3 is formed by coating on the ONO film 2, and the resist film 3 is then patterned as shown in FIGS. 34A through 34C so as to have a pattern equivalent to that of the bit line impurity-diffused layer 4. The exposed portion of the silicon oxide film 2c and silicon nitride film 2b, which are components of the ONO film 2, are etched off. Arsenic ions are then doped by ion implantation into the semiconductor substrate 1, where masking is effected by the resist film 3, to thereby form the bit line impurity-diffused layer 4. The dose herein can typically be set to 1×1015 to 3×1015 cm−2 or around.
Next as shown in FIGS. 35A through 35C, the silicon oxide film 5 having a thickness of 400 to 600 nm is grown by wet oxidation on the surface of the bit line impurity-diffused layer 4. Both edges of the ONO film 2 are lifted to some extent.
Then a phosphorus-doped amorphous silicon (DASi) film is grown over the entire surface by the CVD process, and a tungsten silicide (WSi) film is grown further thereon by the CVD process. The thickness of the DASi film is 100 to 150 nm, and that of the WSi film is 100 to 180 nm. Next a resist film is formed by coating on the WSi film, and then patterned so as to have a pattern equivalent to that of the word lines and gate electrodes of transistors in the peripheral circuit area. Then as shown in FIGS. 36A through 36C, the WSi film and DASi film are successively etched off to thereby form the word lines 6 and gate electrodes of transistors (not shown) in the peripheral circuit area. The resist film is then removed, and a new resist film is formed by coating over the entire surface, and patterned so as to have a pattern equivalent to that of the channel stop impurity-diffused layer. Boron ions are then doped by ion implantation into the semiconductor substrate 1, where masking is effected by the resist film, to thereby form the channel stop impurity-diffused layer 7. The dose herein can typically be set to 5×1012 to 1×1013 cm−2 or around. The channel stop impurity-diffused layer 7 is responsible for element isolation between every adjacent bit line impurity-diffused layers 4. It is to be noted that, in the peripheral circuit area, the ONO film 2 is etched off prior to the formation of the DASi film, where masking is effected by a resist film having openings in the peripheral circuit area, the resist mask is then removed, and a gate oxide film (now shown) is formed.
Next, a CVD oxide film is grown in a thickness of 100 to 200 nm on the entire surface, and then anisotropically etched to thereby produce the sidewalls 8 on the lateral faces of the gate electrodes (not shown) of transistors in the peripheral circuit area and of the word lines 6 as shown in FIGS. 37A through 37C. The inter-layer insulating film 9 is then formed over the entire surface, which is followed by formation of wirings (not shown) and so forth. Thus the NOR-type flash memory is fabricated.
FIGS. 38 and 39 are a circuit diagram and a layout chart, respectively, showing a constitution of an AND-type flash memory. FIG. 40A shows a schematic sectional view taken along the line I—I in FIG. 39, FIG. 40B is such that taken along the line II—II in FIG. 39, and FIG. 40C is such that taken along the line III—III in FIG. 39.
In the AND-type flash memory (a second conventional example), as shown in FIGS. 38 and 39, a plurality of bit lines and a plurality of word lines are arranged so as to spatially cross with each other. The source and drain of a double-gate-structured transistor composing one flash memory cell are respectively connected to either of two adjacent bit lines. Unlike the NOR-type flash memory, there are two bit lines between every adjacent transistors, and these transistors are respectively connected to these bit lines. That is, every bit line is commonly possessed only by the transistors aligned along the extending direction of such bit line. The gates of these transistors are connected to the word lines.
As shown in FIG. 39 and FIGS. 40A through 40C, the bit line is composed of a bit line impurity-diffused layer 4 formed in the surficial portion of the semiconductor substrate 1. An element isolation oxide film 12 is formed between every adjacent bit lines (bit line impurity-diffused layers) respectively connected to the different transistors. On the other hand, the word line 6 is composed of a semiconductor film formed over the semiconductor substrate 1 while placing an insulating film in between. More specifically, a tunnel oxide film 13, a floating gate 14 and the ONO film 2 are provided between the channel region (a portion of the semiconductor substrate 1) and the word line 6. The silicon oxide film 5 having a thickness larger than that of the tunnel oxide film 13, the floating gate 14 and the ONO film 2 are provided between the bit line impurity-diffused layer 4 and word line 6. The floating gate 14 is divided for every transistor. The inter-layer insulating film 9 is formed over the entire surface. The area where neither the bit line impurity-diffused layer 4 nor the word line 6 is formed has a channel stop impurity-diffused layer 7 formed therein. It is to be noted that illustration of the insulating films (ONO film 2, inter-layer insulating film 9 and tunnel oxide film 13) other than the silicon oxide film 5 on the bit line impurity-diffused layer 4 are omitted in FIG. 39.
Next, a third conventional example differing in the sectional structure from that of the second conventional example will be explained. The third conventional example is cited from Japanese Laid-Open Patent Publication No. 8-172174. FIGS. 41A through 41C show a constitution of the third conventional example, where FIG. 41A shows a schematic sectional view taken along the line I—I in FIG. 39, FIG. 41B is such that taken along the line II—II in FIG. 39, and FIG. 41C is such that taken along the line III—III in FIG. 39.
While the channel stop impurity-diffused layer 7 is directly formed in the surficial portion of the semiconductor substrate in the second conventional example, the corresponded portion of the semiconductor substrate 1 in the third conventional example has formed therein a groove 15, and the channel stop impurity-diffused layer 7 is formed by oblique angle ion implantation into the bottom and lateral face of the groove 15. There is also provided a thermal oxide film 17 covering the channel stop impurity-diffused layer 7 and a flash memory cell. A CVD oxide film is further formed thereon as an inter-layer insulating film 9.
Next paragraphs will describe a method of fabricating the AND-type flash memory according to the third conventional example. FIGS. 42A, 42B and 42C, and FIGS. 43A, 43B and 43C are schematic sectional views serially showing process steps in the fabrication method of such AND-type flash memory of the third conventional example, where FIGS. 42A and 43A illustrate the area shown in FIG. 41A, FIGS. 42B and 43B illustrate the area shown in FIG. 41B, and FIGS. 42C and 43C illustrate the area shown in FIG. 41C.
In the fabrication of the AND-type flash memory according to the third conventional example, the tunnel oxide film 13 and semiconductor substrate 1 are etched, where masking is effected by the resist film 16 used for patterning the word line 6, ONO film 2 and floating gate 14 to obtain the constitution shown in FIG. 40, and also by the silicon oxide film 5 on the bit line impurity-diffused layer 4, to thereby form the groove 15 as shown in FIGS. 42A through 42C. Then the channel stop impurity-diffused layer 7 is formed by oblique angle ion implantation into the bottom and lateral face of such groove 15. The resist film 16 is then removed.
Then as shown in FIGS. 43A through 43C, the thermal oxide film 17 is grown so as to cover the channel stop impurity-diffused layer 7 and flash memory cell 16, and further thereon the CVD oxide film is formed as an inter-layer insulating film 9, which is followed by formation of wirings and so forth.
A fourth conventional example can be found in Japanese Laid-Open Patent Publication No. 5-275716, which discloses a method by which sidewalls are formed on the lateral faces of the word lines, the semiconductor substrate is etched, where masking is effected by the sidewalls to thereby form grooves, at the bottom of which a channel stop impurity-diffused layer is formed, and bit lines are formed on the lateral faces thereof.
The conventional examples described in the above are, however, disadvantageous in the following points.
In the first and second conventional examples, only the channel stop impurity-diffused layer 7 is in charge of element isolation, which makes it difficult to assure a sufficient level of voltage resistance between bit lines under an environment where the pitch of the bit lines is reduced for a higher level of integration and space saving.
In the third conventional example, the resist film 16 used for patterning the word line 6, ONO film 2 and floating gate 14 is also used directly as a mask in the etching of the tunnel oxide film 13 and semiconductor substrate 1 to thereby form the groove 15. A relatively small thickness of the resist film 16 herein undesirably makes it difficult for the resist film to endure the process, which may result in deformation thereof during the etching. On the contrary, a relatively large thickness of the resist film 16 undesirably makes it difficult to narrow the word line width. Another problem resides in that the channel stop impurity-diffused layer 7 is formed after the groove is formed 15 and to as far as on the lateral faces thereof, which narrows the effective channel width of the flash memory, and consequently reduces current flowing in the transistor.
In the fourth conventional example, the gate electrodes of the individual memory cells are independent from each other within a layer in which the gate electrodes per se are formed. The bit lines are provided, as described in the above, on the lateral faces of the grooves. Such constitution and the method of fabricating thereof is not directly applicable to the flash memory of which word lines and gate electrodes or control gates are composed of the same layer.